The invention relates to controlling memory access in a multiprocessor system.
Multiprocessor architectures have at least a first processor and a second processor, and a memory area to which each of these processors have access. One of the processors at a time is allowed access to the memory. Access to the memory area can be effected by appropriately programmed or fashioned hardware architecture.
In general, the computing power of a system that is built on discrete components or implemented with an integrated circuit is continually enhanced. The processors in the system can be improved or driven at higher clock speeds for this purpose. It is also possible to increase the number of processors or processor kernels. Because it is not always possible to boost the power of the individual processor kernel, more and more often a plurality of processors or processor kernels, which are capable of processing the required computational steps in parallel with one another, are placed in one system.
A problem in such arrangements is that between the individual processors an interface is needed via which the processors can exchange data. A memory having a memory area that all processors can access is preferably used as interface for this purpose.
As known, dual-port RAM (random access memory) can be accessed simultaneously from two sides by two processors. In order to make this possible, such a memory exhibits separate address and data bus systems as well as arbitration logic, which initiates appropriate collision-prevention actions in the case of simultaneous write operations. Such a dual-port RAM is disadvantageously larger than a normal RAM, so that a larger footprint area is required. In addition, the expensive arbitration logic must prevent simultaneous writing to the same RAM cell, that is, to the same memory area at the same time by both processors. Usually one of the two processors is halted by the arbitration logic in case of a conflict.
Also known is the use of a separate arbitration logic in conjunction with a RAM that is subdivided into smaller blocks of individual memory areas. If a plurality of processors want to access the same block at the same time, only one of these processors receives write/read permission. The other processors are halted. This requires an expensive logic in the processor kernels and in the driving of the RAMs.
RISC computing systems have a reduced instruction set. In computers having a corresponding processor architecture, any individual instruction executes only relatively simple operations. In such a processor architecture, an individual processor program or an individual program sequence is allocated to each one of the processors. Each of these program sequences uses corresponding instructions to control the processing of data as well as memory accesses to a memory area individually allocated to the processor and also to memory areas used in common by a plurality of processors. In the program sequence there can also be jumps, which relocate the processing sequence of the allocated processor from one program address to another program address within the program sequence.
There is a need for improved memory access control in a multiprocessor architecture.